1. Field of the Invention
The present invention relates to an electronic device having a transfer circuit which transfers a digital transmit signal output from a driver to a receiver via signal lines.
2. Description of the Related Art
FIG. 1 is a circuit diagram of an example of a conventional electronic device. The electronic device includes a CMOS differential driver 3 and a CMOS differential receiver 4. The CMOS driver 3 converts a digital transmit signal into complementary transmission digital signals CS and /CS, which are output to signal lines 1 and 2, respectively. The CMOS differential receiver 4 receives the complementary digital transmit signals CS and /CS transferred over the digital signal RS corresponding to the digital transmit signal TS.
The CMOS differential driver 3 includes a CMOS driver 5, which outputs the positive phase digital transmit signal CS which is in phase with the digital transmit signal TS. The CMOS driver 5 includes an n-channel MOS (nMOS) transistor 6 serving as a pull-up element, and a p-channel MOS (pMOS) transistor 7 serving as a pull-down element. The CMOS differential driver 3 includes a CMOS inverter 8, which includes a pMOS transistor 9 serving as a pull-up element, and an nMOS transistor 10 serving as a pull-down element.
The CMOS differential receiver 4 includes a CMOS driver 11, which receives the in-phase phase digital transmit signal CS transferred over the signal line 1. The CMOS driver 11 includes an nMOS transistor 12 serving as a pull-up element, and a pMOS transistor 13 serving as a pull-down element. The CMOS differential receiver 4 includes a CMOS inverter 14, which receives the anti-phase digital transmit signal /CS transferred over the signal line 2. The CMOS inverter 14 includes a pMOS transistor 15 serving as a pull-up element, and an nMOS transistor 16 serving as a pull-down element.
In the electronic device thus configured, when the digital transmit signal TS switches from the low level to the high level, the nMOS transistor 6 of the CMOS driver 5 is turned ON, and the pMOS transistor 7 is turned OFF. Further, the pMOS transistor 9 of the CMOS inverter 8 is turned OFF and the nMOS transistor 10 thereof is turned ON.
Hence, a charge which switches the input terminal of the CMOS driver 11 to the high level from the low level is supplied to the signal line 1 via the CMOS driver 5, and a charge which switches the input terminal of the CMOS inverter 14 to the low level from the high level is drawn to the ground from the signal line 2 via the CMOS inverter 8.
The above phenomenon can be understood so that positive signal energy which changes the input terminal of the CMOS driver 11 from the low level to the high level is supplied to the signal line 1 from the CMOS drier 5 and negative signal energy which changes the input terminal of the CMOS inverter 14 from the high level to the low level is supplied to the signal line 2 from the CMOS inverter 8.
When the input terminal of the CMOS driver 11 switches from the low level to the high level and the input terminal of the CMOS inverter 14 switches from the high level to the low level, the nMOS transistor 12 of the CMOS driver 11 is turned ON and the pMOS transistor 13 is turned OFF. Further, the pMOS transistor 15 of the CMOS inverter 14 is turned ON, and the nMOS transistor 16 thereof is turned OFF.
Hence, the outputs of the CMOS driver 11 and the CMOS inverter 14 are turned to the high level from the low level. Thus, the receive digital signal RS output by the CMOS differential receiver 4 is switched to the high level from the low level. Thus, the CMOS differential receiver 4 substantially receives the digital transmit signal TS.
In contrast, when the digital transmit signal TS switches from the high level to the low level, the nMOS transistor 6 of the CMOS driver 5 is turned OFF, and the pMOS transistor 7 is turned ON. Further, the pMOS transistor 9 of the CMOS inverter 8 is turned ON, and the nMOS transistor 10 thereof is turned OFF.
Hence, a charge which switches the input terminal of the CMOS driver 11 from the high level to the low level is drawn to the ground from the signal line 1 via the CMOS driver 5, and a charge which switches the input terminal of the CMOS inverter 14 from the low level to the high level is supplied to the signal line 2 from the CMOS inverter 8.
The above phenomenon can be considered so that negative signal energy which changes the input terminal of the CMOS driver 11 from the high level to the low level is supplied to the signal line 1 from the CMOS driver 5, and positive signal energy which changes the input terminal of the CMOS inverter 14 from the low level to the high level is supplied to the signal line 2 from the CMOS inverter 8.
When the input terminal of the CMOS inverter 11 switches from the high level to the low level and the input terminal of the CMOS inverter 14 switches from the low level to the high level, the nMOS transistor 12 of the CMOS driver 11 is turned OFF and the pMOS transistor 13 thereof is turned ON. Further, the pMOS transistor 15 of the CMOS inverter 14 is turned OFF and the nMOS transistor 16 thereof is turned ON.
Hence, the outputs of the CMOS driver 11 and the CMOS inverter 14 are switched from the high level to the low level. Hence, the receive digital signal RS output by the CMOS differential receiver 4 is switched from the high level to the low level. Thus, the CMOS differential receiver 4 substantially receives the digital transmit signal TS.
As described above, in the conventional electronic device shown in FIG. 1, complementary signal energy is supplied to the signal lines 1 and 2 from the CMOS differential driver 3 when the digital transmit signal TS changes, so that the complementary digital transmit signals CS and /CS derived from the digital transmit signal TS are transferred to the CMOS differential receiver 4 via the signal lines 1 and 2.
When the signal lines 1 and 2 are equal-length parallel lines so that the coupling coefficient is close to 1, the signal lines 1 and 2 form a transfer path in which the electromagnetic field is approximately closed. Hence, the complementary digital transmit signals CS and /CS are transferred in a mode close to a TEM (Transversed Electromagnetic Mode), and thus speeding up of signal transfer can be achieved.
However it is to be noted that, when the complementary digital transmit signals CS and /CS are transferred to the CMOS differential receiver 4 from the CMOS differential driver 3, complementary signal energy supplied to the signal lines 1 and 2 from the CMOS differential driver 3 are supplied from the power supply line. Hence, in order to further speed up the signal transfer, it is required to supply the complementary signal energy to the CMOS differential driver 3 from the power supply line at a higher speed. However, in this regard, there is no proposal.
It is an object of the present invention to provide an electronic device or apparatus equipped with a CPU and a plurality of memories in which a signal can be transferred between the CPU and the memories at a higher speed.
The above object of the present invention is achieved by an electronic device comprising: a wiring board; at least one pair of signal lines that are provided on the wiring board in parallel and have equal lengths; a chip that is mounted on the wiring board and includes at least one differential driver which outputs complementary digital transmit signals to the above-mentioned at lest one of the pair of lines; and a pair of power system lines through which first and second power supply voltages are supplied to the above-mentioned at least one differential driver, said pair of power system lines being parallel to each other and having an equal length.
When a transmit digital signal applied to the differential driver changes its level, resultant complementary signal energy which changes the levels of input terminals of a differential receiver connected to the pair of signal lines is supplied thereto by the differential driver. The above complementary signal energy is supplied to the differential driver via the power system lines.
The power system lines are parallel to each other and have an equal length, and thus function as a transfer path in which the electromagnetic field is approximately closed with respect to the complementary signal energy to be supplied to the differential driver. Hence, the complementary signal energy to be supplied to the differential driver can be transferred thereto at a high speed without any attenuation. Thus, the complementary digital transmit signals can be transferred over the pair of signal lines at a high speed.
The above-mentioned objects of the present invention are also achieved by an electronic device comprising: a wiring board; at least one signal line formed on the wiring board; a chip that is mounted on the wiring board and includes a driver which outputs a non-differential digital transmit signal; and a first capacitor connected between power system lines formed on the chip via which lines first and second power supply voltages are supplied to the driver, the power system lines being parallel to each other and having an equal length.
With the above configuration, before complementary signal energy is supplied to the differential driver via the power system lines, complementary signal energy can be supplied thereto from the first capacitor. Hence, the transmit digital signal can be transferred over the signal line at a high speed.
The above-mentioned objects of the present invention are also achieved by an electronic device comprising: a wiring board having first and second surfaces; a CPU mounted on a chip mounting area provided on a central position of the first surface of the wiring board; memories mounted on at least one of the first and second surfaces of the wiring board; and first, second, third and fourth groups of respective parallel signal lines having an equal length. The first, second, third and fourth groups respectively extend on the first surface from sides of the chip mounting area in four orthogonal directions, penetrate through the wiring board, and extend on the second surface toward a center thereof. The memories located at an equal distance from connections between terminals of the CPU and the first through fourth groups of signal lines along the four orthogonal distances are of an identical type and are connected to corresponding groups of signal lines.
Hence, it is possible to minimize the lengths of the signal lines of an electronic device which is formed by a single wiring board and is required to connect a CPU and memories accessed thereby by means of equal-length parallel lines. Hence, signals can be transferred between the CPU and the memories at a high speed.
The above-mentioned objects of the present invention are also achieved by an electronic device comprising: first and second wiring boards respectively having first and second surfaces; a CPU mounted on a chip mounting area provided on a central position of the first surface of the first wiring board; memories mounted on at least one of the first and second surfaces of the wiring board; and first, second, third and fourth groups of respective parallel signal lines having an equal length. The first, second, third and fourth groups respectively extend on the first surface from sides of the chip mounting area in four orthogonal directions and extending on the second surface toward a center thereof. The memories located at an equal distance from connections between terminals of the CPU and the first through fourth groups of signal lines along the four orthogonal distances are of an identical type and are connected to corresponding groups of signal lines.
Hence, it is possible to minimize the lengths of the signal lines of an electronic device which is formed by two wiring boards and is required to connect a CPU and memories accessed thereby by means of equal-length parallel lines. Hence, signals can be transferred between the CPU and the memories at a high speed.
The aforementioned objects of the present invention are achieved by an electronic device comprising: first and second semiconductor substrates respectively having first and second surfaces; a CPU mounted on a chip mounting area provided on a central position of the first surface of the first semiconductor substrate; memories mounted on at least one of the first and second surfaces of the semiconductor substrate; and first, second, third and fourth groups of respective parallel signal lines having an equal length. The first, second, third and fourth groups respectively extend on the first surface from sides of the chip mounting area in four orthogonal directions and extend on the second surface toward a center thereof. The memories located at an equal distance from connections between terminals of the CPU and the first through fourth groups of signal lines along the four orthogonal distances are of an identical type and are connected to corresponding groups of signal lines.
Hence, it is possible to minimize the lengths of the signal lines of an electronic device which is formed by two semiconductor substrates and is required to connect a CPU and memories accessed thereby by means of equal-length parallel lines. Hence, signals can be transferred between the CPU and the memories at a high speed.